In order to increase the density and performance of integrated circuits (ICs), device sizes are becoming smaller and operating voltages are becoming lower. This creates a problem in that these more advanced ICs are often required to interface with older technology ICs, such as I/O devices. The older technology ICs typically operate at voltages above those sustainable for the gate oxides of the more advanced ICs. In other words, the higher operating voltages of the older technology ICs are not compatible with the lower operating voltages of the more advanced ICs. The gate oxide of a lower voltage device cannot withstand the higher voltage of an older technology device, and thus wears out much too quickly.
The solution is to provide a way in which two or more gate oxide thicknesses can be produced on the same wafer. Thin oxide devices can be produced to implement high-speed advanced logic, and thicker oxide devices can be produced to interface with older technology devices.
Two prior art processes currently exist which allow two gate oxide thicknesses to be produced on the same wafer. The first process includes growing an oxide of a first thickness, applying photoresist, and then etching away the oxide any place where a thinner film is desired. This results in some areas with an oxide already in place, and some areas that are just bare silicon. Next, a second oxide is grown on the wafer. The areas that already had some oxide in place now have an even thicker oxide, and the areas that were just bare silicon have an oxide that is only as thick as the second oxide layer. The result is two gate oxide thicknesses on the same wafer, where the thicknesses can be adjusted as necessary. The problem with this prior art approach is that photoresist processing is performed on top of the first oxide and next to the bare silicon where the second oxide is going to be grown. This tends to be a very defective process.
A second prior art process for providing two gate thicknesses on the same wafer includes the following steps:
1. Grow a first gate oxide layer.
2. Deposit a first poly-silicon layer.
3. Apply a block mask.
4. Etch away the first poly-silicon layer and the first gate oxide (note that the etching is done wherever the second gate oxide type is desired).
5. Strip the block mask.
6. Grow a second gate oxide layer.
7. Deposit a second poly-silicon layer.
8. Apply a block mask.
9. Etch away the second poly-silicon layer and the second gate oxide wherever it is desired that the first poly-silicon layer be the gate contact.
10. Strip the block mask.
11. Continue with normal wafer processing.
While the second prior art approach does not create the number of process defects found in the first prior art approach, it can be an expensive and time-consuming process. Accordingly, it would be desirable to have a less expensive method for creating two or more gate oxide thicknesses on the same wafer. It would also be desirable to have a method which is less prone to process defects.